Digital front end processor and audio decoder sharing a single external memory

ABSTRACT

A data processing device for taking out necessary packet data from a sector in which a plurality of packet data exist in a mixed manner includes an audio decoder unit that has, in parallel, an audio packet extraction unit for extracting an audio packet made up of audio data with respect to an input of sector data from an external memory connected to a front-end processor unit, a supplementary packet extraction unit for extracting a supplementary packet made up of supplementary data, and a frame information extraction unit. Thus, when collectively providing the front-end processor unit and the audio decoder unit on one chip, a buffer memory for the frame state can be omitted.

TECHNICAL FIELD

This invention relates to a data processing device and a data processingmethod, and particularly to a data processing device and a dataprocessing method for taking out necessary packet data from a sector inwhich a plurality of types of packet data exist in a mixed manner.

BACKGROUND ART

Conventionally, compact discs (CD) have been broadly used on whichdigital audio data having a sampling frequency fs of approximately 44.1kHz with each sample having 16 bits for each channel are recorded. Onthe other hand, super audio compact discs (SACD) generated by the DSD(direct stream digital) system have been proposed on which audio streamdata of the 1-bit system having a very high sampling frequency, forexample, a frequency which is 64 times the sampling frequency fs of anordinary CD, are recorded.

As will be described later, as over-sampling and ΔΣ modulation with 64fs are performed on an input signal, a 1-bit audio digital signal isobtained. In a system of the CD format, decimation from a 1-bit signalto a multi-bit PCM code is carried out immediately after that, whereason a SACD employing the DSD system, a 1-bit audio signal is directlyrecorded.

An audio data reproducing device for reproducing a 1-bit audio signalfrom a SACD will now be described. This audio data reproducing devicehas a structure as shown in FIG. 1.

On a SACD 1 from which data is reproduced by the audio data reproducingdevice shown in FIG. 1, a 1-bit audio signal is directly recorded asdescribed above. The 1-bit audio signal recorded on the SACD 1 isgenerated by a ΔΣ modulator based on the DSD system as shown in FIG. 2.In the ΔΣ modulator, an adder 121 calculates a differential signalbetween the input signal as an audio signal inputted through an inputterminal 120 and a 1-bit pulse string, and an integrator 122 integratesthe differential signal. In this case, an audio band error is extracted.A process of converting this signal to a 1-bit pulse output by aquantizer 123 and feeding back the error again is repeated many times.Thus, a 1-bit audio signal is generated.

The SACD 1, on which the 1-bit audio signal is recorded, is mounted on adisc table of the audio data reproducing device shown in FIG. 1 and isrotated, for example at a constant linear velocity by a spindle motor,not shown. The SACD 1, which is being rotated, is irradiated with areproducing laser beam emitted from an optical pickup 102 and the 1-bitaudio signal is read out from the SACD 1. The optical pickup 102 ismoved between the inner and outer circles of the SACD 1 by a feedmechanism, not shown, and thus scans the signal recording area of theSACD 1 with the reproducing laser beam to read the 1-bit audio signalrecorded on the SACD 1.

The signal read out by the optical pickup 102 is supplied to an RFamplifier 103. An RF signal outputted from the RF amplifier 103 issupplied to a front-end processor unit 104. The front-end processor unit104 uses an external memory 105 as a buffer for data or as a work areaduring error correction processing. The front-end processor unit 104performs demodulation and error correction processing on the RF signalto generate sector data with a fixed length of 2064 bytes and suppliesthe sector data toe an audio decoder unit 106 on the subsequent stage.

The audio decoder unit 106 receives, by 1 byte each, the sector data ofa fixed length of 2064 bytes supplied from the front-end processor unit104. In the audio decoder unit 106, an audio header starting at, forexample, the 13th byte from the leading part of each sector is analyzedby an audio header analyzer 111 and the data is recorded by frame intoeach block of an external memory 107, with each frame having 1/75seconds.

The data recorded by frame in each block of the external memory 107 isdecoded by a compression decoder 112 inside the audio decoder unit 106.After that, fader processing is performed on the data by a fader 113,when necessary, and the data is then converted to an analog audio signalby a D/A converter 108. The analog audio signal is supplied to anexternal amplifier, a speaker and the like through an output terminal109.

When the data is recorded by frame into each block of the externalmemory 107 with each frame having 1/75 seconds while the audio headeranalyzer 111 analyzes the audio header, areas for recording an audioframe (FA) formed by connecting audio packets and a supplementary frame(FS) formed by connecting supplementary packets in the sector recordedin the external memory 105 shown in FIG. 3 are also separated in eachblock of the external memory 107 shown in FIG. 4. A padding packet andstuffing data shown in FIG. 3 are not recorded in each block, as shownin FIG. 4. The purpose of classifying the data by type into audio dataand supplementary data and buffering the data by frame (FA, FS) in FIG.4 is to quickly send the data to the compression decoder 112 on thesubsequent stage which requests only frame-based audio data.

In each frame shown in FIG. 4, data is recorded with frame informationadded thereto, the frame information consisting of error information anda time code. The error information indicates that a frame including datawhich could not be error-corrected by the front-end processor unit 104is an error frame. Since the time code is incremented by frame,discontinuity of frames can be detected by comparing the preceding andsubsequent time codes.

The audio decoder unit 106 reads in advance the frame information IFrecorded in the external memory 107 and therefore can send an error flagto the fader 113 before outputting a discontinuous point of frames dueto an error frame, cue/review and tune selection, or the last data ofthe final frame in which recording is completed in the buffer, as a SDSsignal. Therefore, the fader 113 can perform gradually attenuatedfade-out processing on the DSD output, thus preventing occurrence of astrange sound.

In this manner, in the audio data reproducing device having thestructure as shown in FIG. 1, the front-end processor unit 104 and theaudio decoder unit 106 need the external memory 105 and the externalmemory 107, respectively.

Meanwhile, on the assumption that an IC for the front-end processor unit104 and an IC for the audio decoder unit 106 are collectively providedon one chip in the above-described audio data reproducing device shownin FIG. 1, if a single external memory is used instead of the externalmemories 105 and 107 which are conventionally used by the front-endprocessor unit 104 and the audio decoder unit 106, respectively, thereare advantages such as reduction in cost, reduction in powerconsumption, decrease in the number of IC pins and reduction in theboard area.

If the conventional function of the external memory 105 connected to thefront-end processor unit 104 and the function of the external memory 107connected to the audio decoder unit 106 are to be provided in a newsingle memory by dividing the area of the memory on the basis of theaddress, as shown in FIG. 5, the frame state will be buffered afterbuffering of the sector status, and therefore the number of accesses tothe memory increases. To guarantee the number of accesses, the frequencyof a block for generating a control signal of the memory must be raisedor the circuit within the IC must operate at high speed. Moreover, thepriority control for the access right to the memory is complicated andthe number of accesses to continuous addresses is reduced. Therefore,the advantage of the high-speed page mode cannot be fully utilized.

DISCLOSURE OF THE INVENTION

In view of the foregoing status of the art, it is an object of thepresent invention to provide a data processing device and a dataprocessing method which enable collective provision of the externalmemories connected to the ICs of the front-end processor unit and theaudio decoder unit, on one chip, by eliminating a buffer memory for theframe state.

In order to achieve the above-described object, a data processing deviceaccording to the present invention comprises: sector data generationmeans for performing predetermined signal processing on an input signaland thus generating fixed-length sector data for forming avariable-length frame; sector data storage means for storing the sectordata generated by the sector data generation means; main packetextraction means for extracting main packet data from the sector datastored in the sector data storage means; and supplementary packetextraction means for extracting supplementary packet data from thesector data stored in the sector data storage means.

In the data processing device according to the present invention, mainpacket extraction means and supplementary packet extraction means areprovided in parallel for extracting only specific types of packets, thatis, main packet data and supplementary packet data, from data in which aplurality of types of packets exist in a mixed manner, and prioritycontrol of data request signals outputted from these packet extractionmeans is carried out. Thus, various packet data can be supplied to thesubsequent block when necessary, without using a large-capacity databuffer.

Moreover, in this data processing device, an error signal for errorfading can be sent to fade processing means at appropriate timing.

A data processing method according to the present invention comprises: asector data generation step of performing predetermined signalprocessing on an input signal and thus generating fixed-length sectordata for forming a variable-length frame; a main packet extraction stepof extracting main packet data from sector data storage means in whichthe sector data generated by the sector data generation step is stored;a supplementary packet extraction step of extracting supplementarypacket data from the sector data storage means; and a frame informationextraction step of extracting frame information related to thevariable-length frame from the sector data storage means; wherein anorder of priority is set with respect to data request signals outputtedfrom the main packet extraction step, the supplementary packetextraction step and the frame information extraction step, andrespective packet data corresponding to the data request signals areoutputted from the sector data storage means in accordance with theorder of priority.

The other objects of the present invention and specific advantagesprovided by the present invention will be further clarified from thefollowing detailed description of the structure with reference to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a conventional audio data reproducingdevice.

FIG. 2 is a block diagram showing a ΔΣ modulator based on the DSDsystem.

FIG. 3 shows sector data stored in an external memory connected to afront-end processor unit constituting the audio data reproducing deviceshown in FIG. 1.

FIG. 4 shows data recorded by 1/75-second frame each, into a block of aexternal memory connected to an audio decoder unit constituting theaudio data reproducing device shown in FIG. 1.

FIG. 5 shows division of a memory area by address in which the externalmemory connected to the front-end processor unit of the audio datareproducing device shown in FIG. 1 and the external memory connected tothe SACD decoder unit are collectively provided.

FIG. 6 is a block diagram showing an optical disc reproducing device towhich the present invention is applied.

FIG. 7 shows the data structure of a SACD-standard optical disc fromwhich data is reproduced by the optical disc reproducing deviceaccording to the present invention.

FIG. 8 shows a volume space of the SACD-standard optical disc.

FIG. 9 shows the corresponding relation between TOC and information onthe SACD-standard optical disc.

FIG. 10 is a block diagram showing the detailed structure of a dataprocessing device constituting the optical disc reproducing deviceaccording to the present invention.

FIG. 11 shows the syntax of an audio header (Audio_Header).

FIG. 12 shows the syntax of frame information (Frame_Info).

FIG. 13 is a view for explaining a first specific example of processingto confirm that a sector constituting a frame Fn+1 next to the currentlyprocessed frame Fn is prepared in all external memories.

FIG. 14 is a view for explaining a second specific example of processingto confirm that a sector constituting a frame Fn+1 next to the currentlyprocessed frame Fn is prepared in all external memories.

FIGS. 15A to 15G are timing charts for explaining the operations of theaudio data reproducing device when an error frame, discontinuous frames,and a final frame exist in frame data.

FIG. 16 is a view for explaining the details of a phenomenon of framediscontinuity.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an optical disc reproducing device which has therein a dataprocessing device according to the present invention and carries out adata processing method according to the present invention will bedescribed with reference to the drawings.

The optical disc reproducing device to which the present invention isapplied has a structure as shown in FIG. 6 and carries out reproductionof data from a SACD-standard optical disc 1 on which a 1-bit audiosignal generated by a ΔΣ modulator based on the DSD system is directlyrecorded.

The optical disc reproducing device has an optical pickup 2 for readingout a pit signal from the SACD-standard optical disc 1, an RF amplifier3 for amplifying the pit signal read out by the optical pickup 2, aone-chip data processing device 4 including a front-end processor unit 4a and an audio decoder unit 4 b, which will be described later, and aD/A converter 6 for converting audio data obtained by the dataprocessing device 4 to an analog audio signal and supplying the analogaudio signal to an output terminal 7, as shown in FIG. 6.

The front-end processor unit 4 a constituting the one-chip dataprocessing device 4 performs demodulation and error correctionprocessing on the RF signal amplified by the RF amplifier 3 and thusgenerates sector data with a fixed length of 2064 bytes. The front-endprocessor unit 4 a is connected with an external memory 5. The front-endprocessor unit 4 a uses the external memory 5 for temporarily storingsector data and also uses the external memory 5 as a work area duringthe error correction processing. As the external memory 5, a synchronousDRAM is used.

The audio decoder unit 4 b constituting the one-chip data processingdevice 4 decodes the sector data with a fixed length of 2064 bytessupplied from the front-end processor unit 4 a and supplies the decodeddata to the D/A converter 6. The audio decoder unit 4 b does not need anexternal memory for buffering the frame state which would be used in aconventional SACD audio decoder. The audio decoder unit 4 b also avoidsusing a built-in SRAM of its IC as a buffer. Since one frame consists of16 sectors at the maximum, even a buffer for one frame needs a capacityof approximately 32 kbytes and therefore the built-in SRAM of the ICcannot be used as a frame buffer.

The structure of the SACD-standard optical disc 1 will now be describedwith reference to FIG. 7. This optical disc 1 is sectioned into threeareas, that is, a lead0in zone, a data zone, and a lead-out zone,sequentially from the inner circumferential side to the outercircumferential side. These areas are collectively referred to as aninformation zone.

The optical disc 1 has a ROM structure so that data is recorded bysector in the data zone. Each sector has a physical address number(physical sector number) and a space for 2064 bytes per sector isprepared so that effective data of 2048 bytes can be recorded in eachsector.

By using a logical address number (logical sector number) starting a “0”instead of the physical address number for the data zone, applicationdata to be recorded in a volume space is managed.

The volume space is divided into five areas in accordance with the useof data, as shown in FIG. 8. Specifically, the five areas are a filesystem area, a master TOC area, a 2-channel stereo area, a multi-channelarea, and an extra data area.

The file system area is an area having a file system recorded therein,which enables access in consideration of the use of the computer.

In accordance with the SACD standard, a dual TOC structure is employedwhich is made up of a master TOC and an area TOC based on and developedfrom the idea of TOC in a CD. In the master TOC area, the same masterTOC indicating album information and disc information is recorded threetimes, as shown in FIG. 9. The area TOC will be described later.

In accordance with the SACD standard, a multi-channel mode as well as2-channel stereo mode is possible and two independent area are prepared,that is, the 2-channel stereo area and the multi-channel area. As forthe disc, three types of modes are possible, that is, only the 2-channelstereo mode, only the multi-channel mode, and both the 2-channel stereomode and the multi-channel mode. In both the 2-channel stereo mode andthe multi-channel mode, the DSD (direction stream digital) recordingsystem is used as the coding system. Each channel constantly has datawhich is sampled by 1-bit, 64 Fs sampling (Fs=44.1 kHz).

In the volume space, the 2-channel stereo area and the multi-channelarea have audio areas, respectively. For example, in the audio area ofthe multi-channel area, a track area having recorded therein a musicsignal based on the DSD (direction stream digital) recording system isarranged, and an area TOC-1 and area TOC-2 having stored therein thesame data related to area information and track information are arrangedbefore and after the track area, as shown in FIG. 9.

In the track area, a music signal based on the DSD recording system isrecorded, as described above. Actually, however, audio data, which willbe described later, and supplementary data are independently recorded.The supplementary data is equivalent to a subcode in a CD (signal thatcan be read out synchronously with the music signal). An independentdata area is secured for the supplementary data. The audio data issampled constantly under the same conditions for the respective channelsin order to maintain predetermined quality, whereas the data quantity ofthe supplementary data can be selected in a scalable manner depending onthe use.

The detailed structure of the data processing device 4 according to thepresent invention will now be described with reference to FIG. 10.

The front-end processor unit 4 a constituting the data processing device4 shown in FIG. 10 has a sector address continuity detection unit 41 todetect whether the addresses of sectors stored in the external memoryare continuous or not. If frame data is jumped in accordance with acue/review operation or a tune selection operation by a user, the sectoraddress numbers become discontinuous.

When continuity of the sector address cannot be detected by the sectoraddress continuity detection unit 41, that is, when discontinuity of thesector address is detected, the result of detection is supplied to aframe information extraction unit 52, which will be described later, viaa priority control unit 42.

The audio decoder unit 4 b has, in parallel, an audio packet extractionunit 43 for extraction an audio packet made up of audio data from asector data input b from the external memory 5 connected to thefront-end processor unit 4 a, a supplementary packet extraction unit 48for extracting a supplementary packet made up of supplementary data, andthe frame information extraction unit 52.

At the leading end of each sector, an audio header (Audio_Header) isstored. To analyze the audio header, the audio packet extraction unit43, the supplementary packet extraction unit 48 and the frameinformation extraction unit 52 independently have header analyzers 43 a,48 a and 52 a, respectively.

Generally, frame data is written over a plurality of sectors. Since theaudio packet extraction unit 43, the supplementary packet extractionunit 48 and the frame information extraction unit 52 reads onlynecessary parts of data and operate independently, these extractionunits do not necessarily process the same sector. Therefore, the audioheader analyzers 43 a, 48 a and 52 a are separately provided.

In the audio header, the type and length of each packet included in thatsector, and information such as whether or not it is the leading packetof the frame are described, as shown in FIG. 11. Particularly, N_Sectorsindicating the number of sectors used in that frame is described in theframe information (Frame_Info), as shown in FIG. 12. The headeranalyzers 43 a, 48 a and 52 a analyze such audio headers.

The audio packet extraction unit 43 is connected to an audio data FIFOregister 44. The audio data FIFO register 44 is connected to acompression decoder 45, which is connected to a fader 46.

The supplementary packet extraction unit 48 is connected to asupplementary FIFO register 49. The supplementary FIFO register 49 isconnected to a supplementary data interface unit 50. The frameinformation extraction unit 52 is connected to the fader 46.

The audio decoder unit 4 b has the priority control unit 42 and gives anorder of priority in accordance with data request signals d1, d2, d3outputted from the audio packet extraction unit 43, the supplementarypacket extraction unit 48 and the frame information extraction unit 52.The audio decoder unit 4 b then select a sector number and a byteaddress c1, c2, c3 from one of the extraction units and outputs a memoryread address a.

Hereinafter, the operation of the data processing device 4 shown in FIG.10 will be described with reference to the above-described FIG. 3. FIG.3 shows sector-based data stored in the external memory 5.

First, the audio packet extraction unit 43 reads only data of an audiopacket from the external memory 5 while analyzing an audio header byusing the header analyzer 43 a. Specifically, from the contents of theaudio header of the present target sector, the type and length of eachpacket included in that sector and information about whether or not itis the leading packet of the frame are analyzed, and a byte addressindicating where the audio packet data is written in the sector iscalculated.

This byte address and the sector number of the present target sector areoutputted, thus controlling the byte address to skip the other packetsthan the audio packet.

Even when reading of all the data of the audio packets included in thetarget sector is completed, if the leading packet of the next frame isnot found, the sector number is incremented and the next sector becomesa target sector. After the audio header of the new target sector isanalyzed, reading of data of the audio packets is continued.

As reading of all the data of the audio packets existing before theleading packet of the next frame is completed, the audio packetextraction unit 43 is on standby for the start of the next frame.

The data which is actually read out from the external memory 5 when thedata request signal d1 from the audio packet extraction unit 43 isselected by the priority control unit 42, is stored into the audio dataFIFO register 44. The compression decoder 45 on the subsequent stagetakes therein effective data stored in the audio data FIFO register 44,when necessary.

As the supplementary packet, padding packet and stuffing data areskipped, the compression decoder 45 can receive the data of a necessaryaudio frame without having to wait even if there is no buffer memory forthe frame state.

The number of stages of the audio FIFO register 44 may be a number whichis enough for supplying data to the compression decoder 45 whileanalyzing the audio header when the audio packet extraction unit 43shifts the read target sector to a new sector. Since the number of timesthe audio header is analyzed in one frame is limited, the audio FIFOregister 44 may have a minimum necessary number of stage inconsideration of this.

The supplementary packet extraction unit 48 reads out only data of asupplementary packet from the external memory 5 while analyzing an audioheader by using the header analyzer 48 a. Specifically, from thecontents of the audio header of the present target sector, thesupplementary extraction unit 48 detects the type and length of eachpacket included in that sector and whether it is the leading packet ofthe frame or not, and calculates a byte address indicating whethersupplementary packet data is written in the sector. This byte addressand the sector number of the present target sector are outputted, andthe byte address is controlled to skip the other packets than thesupplementary packet. Even when reading of all the data of thesupplementary packets included in the target sector is completed, if theleading packet of the next frame is not found, the supplementary packetextraction unit 48 increments the sector number to use the next sectoras a target sector. After analyzing the audio header of the new targetsector, the supplementary packet extraction unit 48 continues readingthe data of the supplementary packets. When reading of all the data ofthe supplementary packets existing before the leading packet of the nextframe is completed, the supplementary packet extraction unit 48 is onstandby for the start of the next frame.

The data which is actually read out from the external memory 5 when thedata request signal d2 from the supplementary packet extraction unit 48is selected by the priority control unit 42, is stored into thesupplementary data FIFO register 49. If there is effective data in thesupplementary data FIFO register 49, the supplementary data interfaceunit 50 on the subsequent stage reads out and outputs the effective datato an output terminal 51.

If there is no particular limitation to timing for the external outputof the supplementary data, the supplementary data FIFO register 49 isnot necessary.

The frame information extraction unit 52 examines whether all thesectors constituting a frame Fn+1, which is next to a frame Fn currentlyprocessed by the audio packet extraction unit 43 and the supplementarypacket extraction unit 48, are prepared in the external memory 5, andwhether these sectors do not include error data, while analyzing theaudio header by using the header analyzer 52 a. Moreover, from theextracted frame information, the frame information extraction unit 52determines whether or not the sector data stored in the external memory5 is the last data of the final frame completed in recording in theexternal memory 5. The frame information extraction unit 52 receives adetection result to the effect that the sector addresses arediscontinuous, from the address continuity detection unit 41 via thepriority control unit 42.

When all the sectors constituting the frame Fn+1 which is next to thecurrently processed frame Fn are not prepared in the external memory 5,or when the sectors include an error frame, or when the sector data isthe last data of the final frame, or when the sector addresses arediscontinuous, the frame information extraction unit 52 supplies anerror signal e to the fader 46 and thus causes the fader 46 to performfade processing on the DSD decode signal from the compression decoder.

A specific example of the processing in the above-described frameinformation extraction unit 52 will now be described with reference toFIGS. 13 to 16.

First, the processing to confirm whether or not all the sectorsconstituting the frame Fn+1, which is next to the currently processedframe Fn, are prepared in the external memory 5, will be described withreference to two cases shown in FIGS. 13 and 14.

In FIG. 13, from the contents of N_Sectors (in this case, 4) indicatingthe number of sectors used in the frame, written in an audio header A_Hof a sector including the leading packet of the frame Fn, the sectornumber k of a sector Sk including the last packet of the frame Fn can becalculated. Therefore, it can be seen that the leading packet of theframe Fn+1 is included in the sector Sk or in a sector Sk+1. In thiscase, since N_Sectors of the frame Fn+1 is written in the audio headerof the sector Sk shown in FIG. 13, it can be seen that the leadingpacket of the frame Fn+1 is also included in the sector Sk. Therefore,as the audio header of the sector Sk is analyzed, the sector number m ofa sector Sm including the last packet of the frame Fn+1 can be foundfrom the contents of N_Sectors (in this case, 4), and it can be seenthat all the sectors from the sector Sk to the sector Sm necessary forreproducing the frame Fn+1 have already been written in the externalmemory 5.

In FIG. 14, since the sector number k of a sector Sk including the lastpacket of the frame Fn can be calculated from the contents of N_Sectors(in this case, 4) and N_Sectors of the frame Fn+1 is not written in theaudio header A_H of the sector Sk, it can be seen that the leadingpacket of the frame Fn+1 is included not in the sector Sk but in asector Sk+1. This is the case where the end of the frame Fn iscoincident with the end of the sector Sk. Therefore, as the audio headerof the sector Sk+1 is analyzed, the sector number m of a sector Smincluding the last packet of the frame Fn+1 can be found from thecontents of N_Sectors (in this case, 3), and it can be seen that all thesectors from the sector Sk+1 to the sector Sm necessary for reproducingthe frame Fn+1 have already been written in the external memory 5.

If the sectors from the sector Sk to the sector Sm have not been writtenyet in the external memory 5, the preparation for the frame Fn+1 is notdone yet and therefore the frame information extraction unit 52 outputsan error signal e to the fader 46.

If these sectors contain error data, the frame Fn+1 is an error frame.Therefore, also in this case, the frame information extraction unit 52outputs an error signal e to the fader 46.

A specific example of the processing in the case where frame datacontain an error signal will now be described with reference to FIGS.15A to 15E.

When it is determined by the frame information extraction unit 52 thatthe frame Fn+1 is an error frame, as shown in FIG. 15A, an error signale shown in FIG. 15C need be outputted to the fader 46 Tf seconds beforethe start of the frame Fn+1, which is a time required for fade-out.Therefore, priority control is performed so that the processing by theframe information extraction unit 52 with respect to the frame Fn+1 endswithin ( 1/75−Tf) seconds from the start of the frame n. Thus, the errorsignal e can be outputted to the fader 46 at appropriate timing evenwithout having a buffer for the frame state.

The fader 46 attenuates the fader gain from 0 db to −∞ db to fade outthe frame data based on the DSD system, as shown in FIG. 15D.

When the error frame Fn+1 ends, the fader 46 is notified of the absenceof the error before the start of the frame Fn+2 and is caused to raisethe fader gain from −∞ db to 0 db, thus fading in the frame data Fn+2.

A specific example of the processing by the frame information extractionunit 52 in the case where a detection result showing discontinuity ofsector addresses is received from the sector address continuitydetection unit 41, will now be described with reference to FIGS. 15B to15E.

This is the processing which occurs when a cue/review or tune selectionoperation is carried out by the user. When there is a discontinuouspoint in the frame data, that is, when it is found that the frame Fn andthe frame Fm are discontinuous as shown in FIG. 15B from the result ofdetection by the sector address continuity detection unit 41, receivedby the frame information extraction unit 52 through the priority controlunit 42, the frame information extraction unit 52 outputs the errorsignal e shown in FIG. 15C to the fader 46 Tf seconds before the startof the frame n+1, which is a time required for fade-out.

In accordance with this timing, the fader 46 attenuates the fader gainshown in FIG. 15D from 0 db to −∞ db to fade out the frame data based onthe DSD system.

This phenomenon of frame discontinuity will be described in detail withreference to FIG. 16.

In FIG. 16, the sector number k of a sector Sk including the last packetof the frame Fn can be calculated from the contents of N_Sectors (inthis case, 4), and it can be seen that the leading packet of the frameFn+1 is included in the sector Sk. Therefore, as the audio header of thesector Sk is analyzed, the sector number m of a sector Sm including thelast packet of the frame Fn+1 can be found from the contents ofN_Sectors (also in this case, not less than 2). However, the next sectoris not a sector Sk+1 but a sector Sj, and the sector numbers arediscontinuous j≠k+1).

Therefore, the frame Fn+1 cannot be reproduced and also a frame F1 isprocessed as an error frame.

When the frame data is jumped in accordance with a cue/review or tuneselection operation as described above, if the sector numbers arediscontinuous, the frame next to the frame Fn is a discontinuous frame.Therefore, again, an error signal is outputted to the fader 46 on thesubsequent stage.

Next, the processing in the case where it is determined from theextracted frame information that the sector data stored in the externalmemory 5 is the last data of the final frame completed in recording inthe external memory 5, will be described with reference to FIGS. 15E to15G. This determination is made as the frame information extraction unit52 reads the time code written in the frame information.

When the final frame exists in the frame data as shown in FIG. 15E, anerror signal e may be outputted to the fader 46 Tf seconds before theend point, which is a time required for fade-out. Thus, the fader 46attenuates the fader gain from 0 db to −∞ db as shown in FIG. 15G inaccordance with that timing and thus fades out the frame data based onthe DSD system.

In the above description, the external memory 5 is externally connectedto the one-chip data processing device 4. However, the external memorymay be provided inside the data processing device.

INDUSTRIAL APPLICABILITY

According to the present invention, as a buffer memory for the framestate is not necessary when collectively providing a front-end processorunit and a SACD decoder unit on one chip, external memories which wouldbe conventionally connected to respective ICs can be provided as asingle memory. Moreover, since the number of accesses to the memory isnot largely different from the number of accesses to the memory whichwould be conventionally connected to the front-end processor unit, ahigh-speed clock need not be used.

1. A data processing device comprising: sector data generation means forperforming predetermined signal processing on an input signal andgenerating fixed-length sector data therefrom for forming avariable-length frame; a single external memory for storing thefixed-length sector data generated by the sector data generation means;main packet extraction means for extracting main packet data from thefixed-length sector data stored in the single external memory;supplementary packet extraction means provided in parallel with saidmain packet extraction means for extracting supplementary packet datafrom the fixed-length sector data stored in the single external memory;and frame information extraction means provided in parallel with saidmain packet extraction means and said supplemetary packet extractionmeans for extracting frame information related to a frame with fixedlength from the fixed-length sector data stored in the single externalmemory.
 2. The data processing device as claimed in clam 1, furthercomprising control means for giving an order of priority to data requestsignals outputted from the main packet extraction means and thesupplementary packet extraction means and causing the single externalmemory to output respective packet data corresponding to the datarequest signals in accordance with the order of priority.
 3. The dataprocessing device as claimed in claim 1, further comprising controlmeans for giving an order of priority to data request signals outputtedfrom the main packet extraction means, the supplementary packetextraction means and the frame information extraction means, and causingthe single external memory to output respective packet datacorresponding to the data request signals in accordance with the orderof priority.
 4. The data processing device as claimed in claim 3,further comprising fade processing means for performing fade-out and/orfade-in processing on the main packet data extracted by the main packetextraction means.
 5. The data processing device as claimed in claim 4,wherein the frame information extraction means controls the fadeprocessing means based on extracted frame information extracted by theframe information extraction means.
 6. The data processing device asclaimed in claim 5, wherein the frame information extraction meansdetects a position of an error frame from the extracted frameinformation for use in controlling the fade processing means.
 7. Thedata processing device as claimed in claim 5, wherein the frameinformation extraction means determines a frame number of thefixed-length sector data stored in the single external memory from theextracted frame information for use in controlling the fade processingmeans.
 8. The data processing device as claimed in claim 5, wherein theframe information extraction means determines whether the fixed-lengthsoccer data stored in the single external memory is last data of a finalframe completed in recording within the single external memory from theextracted frame information for use in controlling the fade processingmeans.
 9. The data processing device as claimed in claim 5, furthercomprising sector address continuity detection means for detectingcontinuity of addresses of the fixed-length sector data stored in thesingle external memory, wherein the frame information extraction meanscontrols the fade processing means in accordance with a result ofdetection from the sector address continuity detection means.
 10. Thedata processing device as claimed in claim 7, wherein the frameinformation extraction means determines whether there is a change inframe number within single sector data based on the extracted frameinformation.
 11. The data processing device as claimed in claim 7,wherein the frame information extraction means determines whetherswitching of continuous frame numbers is coincident with switching ofsector numbers, based on the extracted frame information.
 12. The dataprocessing device as claimed in claim 9, wherein the sector datageneration means incorporates therein the sector address continuitydetection means and is a base for constituting a one-chip componenttogether with the main packet extraction means, the supplementary packetextraction means, the control means, the frame information extractionmeans, and the fade processing means.
 13. A data processing methodcomprising: a sector data generation step of performing predeterminedsignal processing on an input signal and generating fixed-length sectordata therefrom for forming a variable-length frame; a data storage stepof storing the fixed-length sector data generated in said sector datageneration step in a single external memory; a main packet extractionstep of extracting main packet data from the single external memory inwhich the fixed-length sector data generated by the sector datageneration step is stored; a supplementary packet extraction step ofextracting supplementary packet data from the single external memory;and a frame information extraction step of extracting frame informationrelated to the variable-length frame from the single external memory,wherein an order of priority is set with respect to data request signalsoutputted from the main packet extraction step, the supplementary packetextraction step, and the frame information extraction step andrespective packet data corresponding to the data request signals areoutputted from the single external memory in accordance with the orderof priority.
 14. The data processing method as claimed in claim 13,further comprising a fade processing step of performing fade-out and/orfade-in processing on the main packet data extracted at the main packetextraction step.
 15. The data processing method as claimed in claim 14,wherein at the frame information extraction step, the fade processingstep is controlled on the basis of extracted frame information extractedin the frame information extraction step.
 16. The data processing methodas claimed in claim 15, wherein at the frame information extractionstep, a position of an error frame is detected from the extracted frameinformation for use in controlling the fade processing step.
 17. Thedata processing method as claimed in claim 15, wherein at the frameinformation extraction step, a frame number of the fixed-length sectordata stored in the single external memory is determined from theextracted frame information for use in controlling the fade processingstep.
 18. The data processing method as claimed in claim 15, wherein atthe frame information extraction step, whether the fixed-length sectordata stored in the single external memory is last data of a final framecompleted in recording within the single external memory is determinedfrom the extracted frame information for use in controlling the fadeprocessing step.
 19. The data processing method as claimed in claim 15,further comprising a sector address continuity detection step ofdetecting continuity of addresses of the fixed-length sector data storedin the single external memory, wherein at the frame informationextraction step, the fade processing step is controlled in accordancewith a result of detection from the sector address continuity detectionstep.
 20. The data processing method as claimed in claim 17, wherein atthe frame information extraction step, whether there is a change inframe number within single sector data is determined from the extractedframe information.
 21. The data processing method as claimed in claim17, wherein at the frame information extraction step, whether switchingof continuous frame numbers is coincident with switching of sectornumbers is determined from the extracted frame information.